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april 2012 doc id 18249 rev 2 1/22 AN3317 application note pcb guidelines for spear1340 this document applies to th e spear1340 embedded microproce ssor, and is intended to assist experienced printed circuit board designers.
contents AN3317 2/22 doc id 18249 rev 2 contents 1 power integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pcb layer stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 via padstack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 part orientation and placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 ground and power supply connectio ns . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 ddr memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 dram power decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 trace length matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 return path integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 vref routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 observability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 usb routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 usb decoupling and reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 tdr test traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 layer order check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 appendix a low-inductance ca pacitor layout in high- frequency applications 19 a.1 0402 package compact land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 a.2 0402 package low inductance layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AN3317 list of tables doc id 18249 rev 2 3/22 list of tables table 1. trace length matching guidelines, balanced-t configuration . . . . . . . . . . . . . . . . . . . . . . . 12 table 2. usb signal routing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. usb power, ground, and reference guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. 0402 package compact land pattern dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. 0402 packages low inductance layout dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of figures AN3317 4/22 doc id 18249 rev 2 list of figures figure 1. pcb bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. routing topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. data signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. pcb cross section showing minimum spacing dimensions . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. decoupling capacitor layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. 0402 package compact land pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 7. 0402 package low inductance layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
AN3317 power integrity doc id 18249 rev 2 5/22 1 power integrity one of the most important requirements of a reliable high-speed memory interface, and most commonly underestimated, is a low impedance, wide bandwidth power supply at the power and ground balls of the devices. achieving the necessary performance requires mi nimizing all parasitic inductances found in power delivery and grounding connections, exploiting various techniques to provide low impedance paths, and attention to controlling plane resonances. a solid, unbroken ground plane located close to the high-speed devices in the pcb layer stack is critical. the ground plane must not have large gaps anywhere in the area of the interface. be especially aware of overlapping antipads that can create an extended gap in the internal plane layers. a power plane closely spaced to the ground pl ane greatly aids in high-frequency decoupling by providing a low inductance path between a capacitor and the device's power balls. use a low-inductance layout for all high-frequency decoupling capacitors.
pcb layer stacking AN3317 6/22 doc id 18249 rev 2 2 pcb layer stacking include a closely spaced power and ground plane pair; a minimum of 6 layers is recommended, as follows: layer 1: signal layer 2: ground plane, unbroken layer 3: power plane and islands, signals layer 4: signal and power routing layer 5: ground plane, unbroken layer 6: signal select dielectric thickness to support required signal trace characteristic impedances and power plane capacitance and inductance. perform resonance analysis on all plane cavities.
AN3317 via padstack doc id 18249 rev 2 7/22 3 via padstack ensure that via padstack dimensions support density requirements. while meeting pcb fabrication tolerances, make antipad diameters small enough to allow an adequate copper web between the clearance holes of adjacent vias. 3.1 part orientation and placement to optimize routing and signal integrity, give the dram placement and orientation priority over other unassociated components. orient dram components such that the dq balls face the controller. define a dedicated area for the memory system that encloses all components associated with the memory system and excludes all other components and signal routing.
ground and power supply connections AN3317 8/22 doc id 18249 rev 2 4 ground and power supply connections for proper device operation, it is critical to provide a very low impedance, wide bandwidth connection to ground and to the voltage supplies. to achieve this, minimize inductance between the device power and ground balls, and the pcb ground plane and decoupling network. this guideline also applies to other critical components: termination resistors decoupling capacitors ics multiple ground or power pins from the same ic directly connect each ground ball to the pcb ground plane with its own via. do not share vias among multiple ground balls. exception : the center 10 x 10 ground ball grid should have a fully populated ground via grid between the balls, and the surface layers may be filled. directly connect each power ball to the pcb decoupling network with its own via. do not share vias among multiple power balls. exception : when multiple power balls are adjacent to each other and are connected to the same voltage plane, but use the maximum number of vias that space allows. to avoid cross-contamination of ground or power supplies between different devices (for example, an ic and a termination resistor), do not share ground connections among multiple ground or power balls. give each ball and pin its own via to the ground or power plane. do not simply connect power and ground connection s to surface layer copp er fill areas, which are not good low impedance paths at high frequencies. ball-to-via trace : connect each ground and power ball to its via with a short, wide trace. do not simply connect ground or power balls to su rface fill areas; a close, direct via to the ground or power plane is necessary. caution: it is critical to minimize trace length and maximize trace width. in the ball field, make trace length less than 1 mm. outside the ball field, make trace length less than 0.25 mm. make trace width wide. note: when it is not possible to ac hieve a close direct trace, a rela tively high impedance will result. make every effort to minimize trace length, and consider high impedance power connections only for power connections that require lower bandwidth.
AN3317 ddr memory interface doc id 18249 rev 2 9/22 5 ddr memory interface 5.1 dram power decoupling a low impedance, wide bandwidth power delivery network (pdn) is critical for the proper operation of high-spee d ics such as spear and ddr memory . if the pdn impedance is too high or does not have sufficient bandwidth, logic performance is affected. this results in ground and rail bounce, and slower rise and fall times of both io and internal logic, which in turn results in delayed timing of events. these timing delays from inadequate ground and power subtract directly from the specified timing budget, which can result in interface failure. to achieve a low impedance wide bandwidth power delivery network, use the appropriate decoupling capacitors and capacitor layout. a large portion of the power delivery network?s frequency spectrum is above the decoupling capacitor?s series resonant frequency, where they are inductive. the pcb layout for decoupling capacitors is also inductive, and is a larger inductance than that of the capacitors themselves. for ic core voltage and high-speed io supplies (such as ddr) select: capacitors with low inherent inductance (small package size) a lossy dielectric a pcb layout that provides the lowest possible inductance use as many capacitors as can fit in the space available. this creates many parallel paths, reducing the overall inductance seen by the ic. a small capacitor package size and a small layout enable this. 5.1.1 capacitors see also, appendix a: low-inductance capacitor layout in high-frequency applications package : use 0402 package size to minimize mounting inductance. the small 0402 package also frees board space, which is essential in high density areas for more decoupling capacitors and signal routing. capacitance : 100 nf or larger a few capacitors of smaller value will prob ably be necessary for plane resonance suppression. the correct values for these depend on the board layout and stack up, and must be determined individually for each unique pc board. dielectric : x7r or x5r dielectric. do not use y5v dielectric for decoupling mid-frequency applications. decoupling capacitor layout decoupling capacitors layout is extremely important to minimize the induction loop formed between the capacitor and the ic power and ground balls. using the layout guidelines that follow can reduce the capacitor mounting induction loop by 50% or more over a layout with vias at the end of the capacitor lands. if spac e allows, a second pair of vias on the opposite side of the capacitor will reduce the inductance further. closely follow the decoupling layout example on page 10 . place vias on the side of the capacitor lands, not on the ends. locate vias at minimum keepout distance, an d connect them to the capacitor lands with a wide trace ? at least as wide as the via pad.
ddr memory interface AN3317 10/22 doc id 18249 rev 2 place vias of opposite polarity as clos e together as possible (minimum keepout distance), and separate vias of the same polarity as much as possible. decoupling layout example 5.2 signal routing the guidelines in this section are sufficient for initial routing. simulate all layouts with ibis models to verify adequate timing margins. modify layouts as necessary to improve the interface and to comply with a ll timing parameters. modifications can include trace length, width, and spacing, and stack up. 5.2.1 data signal routing where routing density allows, increase trace spacing to reduce crosstalk (see also section 5.4: return path integrity ). do not route any other signals inside or on top of the area reserved for the ddr. maintain adequate separation between ddr signals and any other signals. for traces routed near the edge of a reference plane, keep the trace at least 30 mil from the edge of the reference plane. to minimize reflection, ensure that a ll traces have an impedance of 45 to 55 . 5.2.2 clk/clk# and dqs/dqs# signals route clk/clk# and dqs/dqs# signals as length-matched differential pairs. figure 1 is an example of an effective low-inductance decoupling capacitor placement and mounting layout. figure 1. pcb bottom layer gnd i/o vdd3v3 vdd1v2 ddr phy vdd1v2 ddr i/o vdd1v5 pll avdd2v5 usb vdd3v3 miphy vddpll2v5 miphy vddpll1v2 miphy vddr1v2 usb vdd1v2 usb vdd2v5 vdd i/o gmac vreg2 3v3 in vreg1 3v3 in pll vdd1v2 nand vdd i/o1 nand vdd i/o2
AN3317 ddr memory interface doc id 18249 rev 2 11/22 5.3 trace length matching always use trace length equalization to maximi ze the valid timing window of all signals, and include the trace lengths inside the spear device package. a spreadsheet that compensates for the trace lengths inside the substrate is available to compute the necessary pcb trace length offsets (contact st). fly-by and balanced-t topologies each have advantages and disadvantages. which topology is best suited for a particular application must be evaluated on a case-by-case basis, and take into consideration any other system constraints. 5.3.1 address, control, and command (a/c/c) signal group, fly-by configuration match trace lengths on the address, control, and command trace segments between the spear device and the first memory device in the chain. the spreadsheet mentioned above is the easiest way to compute lengths for the a/c/c signal group between the spear devi ce and the first memory device. match trace lengths for each segment group between memory devices. locate terminations beyond the final memory device in the chain. length matching is not critical between the final memory device and the termination, but keep the termination components reasonably near the final memory device. ensure that the termination resistors have excellent decoupling. 5.3.2 a/c/c signal group, dua l dram balanced-t configuration balanced-t topology does not require term ination resistors (except for clk and nclk). balanced-t topology does require equal length branches on all signals within the a/c/c signal group. signal integrity degrades rapidly with unequal branch lengths, with serious negative effects on signal timing. the spreadsheet mentioned above is the easiest way to compute lengths for the a/c/c signal group. place the differential clock termination resistors near the t junction. for a single rank dual dram configuration, either fly-by or balanced-t topology can be used. 5.3.3 data signal groups provide matched trace lengths for each 8-bit data slice, dm signals, and dqs/dqsn signals. it is not necessary to match the trace lengths of one data slice with the trace lengths of any other data slice, because they are independent from a timing perspective. the spreadsheet mentioned above is the easiest way to compute lengths for each data slice signal group. figure 2 and ta bl e 1 describe the length matching guidelines for a dual dram topology. note: this is a guideline only; perform simulations using ibis models on the actual pcb layout to assess signal integrity and timing margin.
ddr memory interface AN3317 12/22 doc id 18249 rev 2 fly-by topology routes a/c/c signal groups in a daisy chain fashion, with terminations on all signals after the last dram device. data lane slices are routed to individual dram devices. balanced t topology can be used for a/c/c signal groups if only two memory devices are used. figure 2. routing topologies 5.3.4 data signal routing to simplify the routing of the data signals, it is possible to swap data between data slices. but it is mandatory to rout e and connect the spear ddr_dq 0 (ball af2), ddr_dq8 (ball ah3) ddr_dq16 (ball ae8) and data24 (ball ah9) on each lsb ddr data pin. table 1. trace length matching guidelines, balanced-t configuration parameter description maximum unit t mm l1+l2, l1+l3 length matching for all signals 15 ps t mm2,3 |l2-l3| length matching tolerance of branches 30 ps dram1 dram2 dram3 dram1 dram2 addr/con/com dq[15:0] dq[31:16] dq[ecc] dq[15:0] dq[31:16] termination fly-by topology addr/con/com equal length l1 balanced t topology l2 l3 spear1340 spear1340
AN3317 ddr memory interface doc id 18249 rev 2 13/22 figure 3. data signal routing data0 addr9 ncs0 data8 ndqs0 addr2 dqs0 ba2 data3 addr7 data2 addr3 data15 dqs1 data7 data[15..0] data1 addr4 addr0 addr5 ba0 nwe data14 data10 data9 dqm0 addr12 odt0 addr1 data5 ndqs1 data12 addr11 ba1 data13 addr10 data6 data4 data11 addr6 addr8 dqm1 addr13 addr14 ncs1 odt1 ba2 3,4 odt0 3,4 ncs0 3,4 data[15..0] 3 dqs0 3 dqm0 3 ba0 3,4 dqs1 3 ndqs0 3 ndqs1 3 ba1 3,4 dqm1 3 we 3 4 ncs1 3,4 odt1 3,4 spear 1340 u1a ddr_dq0 af2 ddr_dq1 af4 ddr_dq2 af1 ddr_dq3 af5 ddr_dq4 ae1 ddr_dq5 ae6 ddr_dq6 ae2 ddr_dq7 ae4 ddr_dq8 ah3 ddr_dq9 ah2 ddr_dq10 ah6 ddr_dq11 ag1 ddr_dq12 ag5 ddr_dq13 ag2 ddr_dq14 ah5 ddr_dq15 ah1 ddr_dqs0p ae3 ddr_dqs0n af3 ddr_dqs1n ag4 ddr_dqs1p ah4 ddr_dm0 ae5 ddr_dm1 ag3 ddr_addr0 u3 ddr_addr1 w2 ddr_addr2 v2 ddr_addr3 v3 ddr_addr4 y2 ddr_addr5 w1 ddr_addr6 y4 ddr_addr7 v1 ddr_addr8 t1 ddr_addr9 u4 ddr_addr10 aa3 ddr_addr11 v4 ddr_addr12 aa2 ddr_addr13 y1 ddr_ba0 y3 ddr_ba1 w3 ddr_ba2 aa1 ddr_odt0 ac3 ddr_odt1 u2 ddr_addr14 w4 ddr_cs0n ab3 ddr_cs1n u1 ddr we aa4 addr5 addr12 addr2 addr10 addr11 addr6 addr7 addr9 addr3 addr8 addr0 addr1 addr4 data0 data7 data6 data5 data3 data1 data2 data4 ddr3_vref addr13 addr14 ba2 2,4 ba0 2,4 dqm0 2 ncas 2,4 nras 2,4 nwe 2,4 ndqs0 2 ncs0 2,4 addr[14..0] 2,4 dqs0 2 data[7..0] 2 ba1 2,4 ncs1 2,4 ddr3 sdram u2 data0 b3 data1 c7 data2 c2 data3 c8 nf/data4 e3 nf/data5 e8 nf/data6 d2 nf/data7 e7 addr0 k3 addr1 l7 addr2 l3 addr3 k2 addr4 l8 addr5 l2 addr6 m8 addr7 m2 addr8 n8 addr9 m3 addr10/ap h7 addr11 m7 addr12/#bc k7 nwe h3 ba0 j2 ba1 k8 ba2 j3 dm, dm/tdqs b7 nf, nf/ntdqs a7 ndqs d3 dqs c3 nras f3 ncas g3 ncs0 h2 a13 n3 vref_dq e1 vref_ca j8 ncs1 h1 a14 n7 addr10 ba2 addr5 addr2 ba1 addr4 nwe addr11 addr0 addr9 addr7 ba0 addr8 addr3 ncs0 nras addr6 addr1 addr12 data9 data8 data10 data12 data15 data11 data14 data13 addr13 addr14 ncs1 dqm1 2 data[15..8] 2 dqs1 2 ndqs1 2 ddr3 sdram u3 data0 b3 data1 c7 data2 c2 data3 c8 nf/data4 e3 nf/data5 e8 nf/data6 d2 nf/data7 e7 addr0 k3 addr1 l7 addr2 l3 addr3 k2 addr4 l8 addr5 l2 addr6 m8 addr7 m2 addr8 n8 addr9 m3 addr10/ap h7 addr11 m7 addr12/#bc k7 nwe h3 ba0 j2 ba1 k8 ba2 j3 dm, dm/tdqs b7 nf, nf/ntdqs a7 ndqs d3 dqs c3 f3 ncs0 h2 a13 n3 ncs1 h1 a14 n7 r69 2
ddr memory interface AN3317 14/22 doc id 18249 rev 2 5.4 return path integrity to minimize signal delays, significant crosstal k, and timing violations, a continuous path for return current must exist for all dram signals. to simplify return paths, route all signals referenced to a ground plane. do not route any ddr3 signals on top of split planes or copper voids. for traces routed near the edge of a reference plane, keep a minimum of 30 mil between the trace and the edge of the reference plane. signal layer changes the preferred location for layer change vias is near the signal ball under a device, either dram or spear, enabling a signal return pa th through the devi ce ground vias and decoupling capacitors. if layer changes through a via to a different reference plane are necessary away from the devices: provide the layer transitions a nearby path for return current. if both layers are ground, place a return path ground via less than 1 mm from the signal via. avoid sharing return current vias; each signal via should have its own nearby return via (ground via). if multiple signals ch ange layers in close proximity: ? provide each signal via its own return current via. ? use a stagger pattern to separate signal vias (and their return current vias) from other signal vias. ? if routing density prevents a stagger pattern, add as many ground vias as possible among the signal vias. 5.5 vref routing provide an accurate and quiet vref to both the dram and the controller. because of the slope of the signal, a noisy vref effectively introduces jitter, which can be a significant source of jitter-caused timing errors. vref is generated by a precision voltage divider. recommended : use 0.1% tolerance resistors. place a decoupling capacitor very close (within 1 mm) to the vref balls. use good capacitor layout techniques. place the voltage divider resistors close to the dram device to minimize trace length, but not so close that they interfere with other critical signal or power routing. do not route the vref trace near noisy traces or planes. do not place a decoupling capacitor at the junction of the resistors ? only at the vref balls. if the vref trace length must be long, make the divider resistor value close to 2x the characteristic impedance of the vref trace; 150 should work well without consuming too much power. if a long trace, noise coupling, or both is unavoidable between the dram and the controller, it is preferable to generate a separate vref for the dram and the controller.
AN3317 ddr memory interface doc id 18249 rev 2 15/22 5.6 observability for system validation, timing, signal quality, and debugging, it is important to be able to observe certain signals. place test points on any signals or set of signals required for these purposes. always provide a ground via near test points for the probe ground, preferably within 1 mm. very small test point pads can be used, preferably just a signal via. if there is insufficient space, a simple window in the solder mask over a trace provides exposed metal for probing. do not create test point structures that significantly degrade signal quality, such as large test points or stubs. locate test points at both ends of a trace (two test points per signal), as close to the device balls as practical (a via next to the ball is preferable, untented on the bottom layer). in high-speed interfaces, it is especially important to be able to observe signals at both the driving and the receiving end of a trace to validate timing parameters and to quantify driver behavior and reflection. observing a signal at only one end can hide important features that are evident at the other end, even with very short traces as is the case in a point-to-point ddr interface. in a ddr memory interface, the routing and component density is too high to add test points on all signals. a subset of ddr signals with test points is a good compromise. include test points for the following ddr signals in all designs: clk/nclk dqs/ndqs : all data lanes dq : select a small number of signals that represent the best and worst signal paths, at least two dq signals. address and control : select signals of interest that represent the best and worst signal paths.
usb routing AN3317 16/22 doc id 18249 rev 2 6 usb routing ensure that usb signal trace routing follows good high speed pcb rules, and meets the specifications for differential impedance and maximum trace delay between the connector and the spear device. route usb data traces with the shortest, most direct path possible to their connectors. usb data traces should have no resistors. route usb data traces only over ground planes. never route usb data traces across gaps or breaks in the return plane. never route usb data traces under other devices or between the pins of other devices. widely separate usb data vias from other signal vias. if usb data traces must transition layers to a different return plane, place ground vias for the return current very close to the signal vias. figure 4. pcb cross section show ing minimum spacing dimensions table 2. usb signal routing constraints parameter description minimum typical maximum units zo diff differential impedance (1) 1. trace delay between spear device and usb connector ( universal serial bus specification , revision 2.0) 81 90 99 td dev trace delay of device port (1) 1.0 ns td host trace delay of host port (1) 3.0 ns td-match trace length mismatch 0.15 3.8 inch mm ? number or length of stubs 0 ? number of via transitions 1 ? space to adjacent signal traces (2) 2. includes other usb data trace pairs. 3h (3) 3. the same as the units used for h , the thickness of the dielectric se parating the trace from the nearest plane (see figure 4 ), which can vary from board-to-board. ? space to adjacent area fill (4) 4. do not use guard traces or ground flood or fi ll adjacent to high speed signal traces. 3h (3) ? space to edge of return plane 20 h (3)
AN3317 usb routing doc id 18249 rev 2 17/22 6.1 usb decoupling and reference resistor place decoupling capacitors as close as possible to the power balls (preferably directly under the power balls) using short, wide connecting traces. placing decoupling capacitors at a distance degrades performance, which can result in interoperability problems and spec ification compliance violations. table 3. usb power, ground, and reference guidelines pin guideline *vss* connect all vss pins directly to internal pcb ground plane *vdd* connect all vdd pins to 100 nf capacitor under ball using short wide trace usb_txrtune 43.2 resistor to ground
tdr test traces AN3317 18/22 doc id 18249 rev 2 7 tdr test traces add test traces to all pcb designs on all signal layers. it is simple to add a single trace of nominal impedance between 8 to 15 cm long on each signal layer (it does not have to be straight) to all designs, and can it always be placed where it will not impact the functional design, for example, usually along the board perimeter. include a test point pattern that matches your tdr probe. test traces are invaluable in validating pcb impedance parameters. 8 layer order check include a visual feature (stair step numbered windows) to verify layer ordered in all pcb layouts. this is most commonly located along one edge of the board.
AN3317 low-inductance capacitor layout in high-frequency applications doc id 18249 rev 2 19/22 appendix a low-inductance capacitor layout in high-frequency applications figure 5 shows several decoupling capacitor layouts. do not use layouts a or b . these layouts have inherently high inductance, and thus a high impedance at high frequencies. use layout d or e for high frequency decoupling applications. these layouts have low inductance. where space allows, use the 4-via layout (e), which has the lowest inductance but requires more board area. where space does not permit the 4-via layout, the 2-via layout (d) is a good compromise. use layout c as a last resort when there is no space for either layout d or e . figure 5. decoupling capacitor layouts a.1 0402 package compact land pattern an area-efficient compact la nd pattern facilitates pcb layo ut of decoupling capacitors. figure 6 shows a commonly used land pattern. figure 6. 0402 package compact land pattern table 4. 0402 package compact land pattern dimensions dimension distance (mil) a20 b20 c15
low-inductance capacitor layout in high-frequency applications AN3317 20/22 doc id 18249 rev 2 a.2 0402 package low inductance layout figure 2 shows a low inductance layout for a 0402 decoupling capacitor using 2 vias with a 10 mil drill size. note that: vias are placed close to the lands. vias of opposite polarity are place close together. the trace connecting land to via is wide. figure 7. 0402 package low inductance layout table 5. 0402 packages low inductance layout dimensions dimension distance (mil) d (land to hole) typically 8 to 10 (1) 1. the land to hole separation is determi ned by the pcb fabrication tolerances. e (hole to hole) typically 30 (2) 2. minimize this distance, c onsistent with pcb fabrication tolerances . if the capacitor is placed within a bga ball field, make dimension e the same as the ball pitch. f (trace width) 20
AN3317 revision history doc id 18249 rev 2 21/22 revision history table 6. document revision history date revision changes 14-mar-2012 1.0 initial release 06-apr-2012 2.0 update st corporate template
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